Full X86_64 Instruction Set Reference Card

#GP(0)If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. (128-bit operations only) If a memory operand is not aligned on a 16-byte boundary, regardless of segment.#GP(0)If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. (128-bit operations only) If a memory operand is not aligned on a 16-byte boundary, regardless of segment.#SS(0)If a memory operand effective address is outside the SS segment limit.#UDIf EM in CR0 is set. (128-bit operations only) If OSFXSR in CR4 is 0.

  1. X86 Instruction Set Architecture
X64 instruction setSheet

(128-bit operations only) If CPUID feature flag SSE2 is 0.#NMIf TS in CR0 is set.#MF(64-bit operations only) If there is a pending x87 FPU exception.#PF(fault-code)If a page fault occurs.Real-Address Mode Exceptions. #GP(0)(128-bit operations only) If a memory operand is not aligned on a 16-byte boundary, regardless of segment. If any part of the operand lies outside of the effective address space from 0 to FFFFH.#GP(0)(128-bit operations only) If a memory operand is not aligned on a 16-byte boundary, regardless of segment. If any part of the operand lies outside of the effective address space from 0 to FFFFH.#UDIf EM in CR0 is set. (128-bit operations only) If OSFXSR in CR4 is 0.

X86 Instruction Set Architecture

(128-bit operations only) If CPUID feature flag SSE2 is 0.#NMIf TS in CR0 is set.Virtual-8086 Mode ExceptionsSame exceptions as in Real Address Mode.

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